As Moore’s law fades, how can more transistors be fitted onto a chip?
set 19, 2024 01:39
INSIDE A STERILE, cavernous building in the Dutch city of Eindhoven, the latest monster dreamed up by ASML, a maker of chipmaking gear, is quietly humming away. Weighing 150 tonnes and the size of a double-decker bus, the tool offers humans the latest way to do something they have been doing since the ice age—writing on stone, otherwise known as lithography. The stone here is silicon; the writing is done with light.
The machine fires 50,000 droplets of tin into a vacuum chamber every second. A laser heats each drop to 220,000°C, 40 times hotter than the surface of the Sun. This transforms droplets into plasma that emits light of extremely short wavelength (extreme ultraviolet, or EUV). The narrow beam of light is reflected, using a series of mirrors that are smooth down to tens of picometres (trillionths of a metre) to hit a mask that contains blueprints of the chip’s circuits.
The EUV rays bounce from the mask and project the design onto a silicon wafer coated with a thin layer of sensitive material called photoresist. The wafer is moved very precisely so that the pattern can be printed again, and again; a wafer can be used to make hundreds of chips. Typically, the exposed photoresist (hit by the light) is washed off, creating a ‘stencil’ on the silicon wafer. Subsequent machines etch away material, implant ions or deposit metals onto the ‘stencil’ to create a layer of the chip. A new layer of photoresist is then added, a new pattern projected onto it, and a new layer of etching takes place. A modern chip can require dozens of such layers of printing.
The latest EUV lithography machines from ASML cost more than $350m each. They thus highlight a dynamic of the semiconductor industry: as transistors, the main type of electronic component found in chips, have become smaller, the tools and factories to make them have become bigger and pricier. Brian Potter of the Institute for Progress, an American think-tank, estimates that in the late 1960s a semiconductor fabrication plant (or fab) cost about $31m in today’s money to build and equip. The newest fabs that TSMC, a Taiwanese giant, is building in Arizona, will cost $20bn each.
Itsy bitsy teeny weeny
The transistors these fabs now make by the trillion are switches. Each one has terminals called the source and the drain that are separated by a channel of silicon. A third terminal, called the gate, sits atop this channel and regulates the flow of current between the source and drain. When voltage is applied to the gate, current flows from the source to the drain. Without voltage, the current stops. These on and off states correspond to the 1s and 0s of binary notation.
However magical a computer program may be, the hardware it runs on is, at heart, a set of such switches turning on and off according to the way they are tied together by circuitry. Simple circuits called logic gates combine transistors to offer the basic functions of binary logic: AND, in which the output is 1 if both inputs are 1; OR, in which the output is 1 if any input is one; and NOT, in which a 1 becomes a zero (or vice versa). Such logic gates can be combined to form more complex circuits, and these circuits in turn can be combined to form powerful processing chips.
Gordon Moore’s original observation, in 1965, was that as the making of chips got better, the transistors got smaller, which meant you could make more for less. In 1974 Robert Dennard, an engineer at IBM, noted that smaller transistors did not just lower unit costs, they also offered better performance. As the distance between source and drain shrinks, the speed of the switch increases, and the energy it uses decreases. “Dennard scaling”, as the observation is known, amplifies the amount of good that Moore’s law does.
In 1970 the gate length, a proxy for the distance between the source and drain, was ten microns (ten millionths of a metre, or 10,000nm). By the early 2000s this was down to 90nm. At this level, quantum effects cause current to flow between the two terminals even when the transistor is off. This leakage current increases the power used and causes the chip to heat up.
For chipmakers that was an early indication that their long, sort-of-free ride was ending (see chart). Transistors could still be made smaller but the leakage current placed a limit on how low a chip’s voltage could be reduced. This in turn meant that the chip’s power could not be reduced as before. This “power wall” marked the end of Dennard scaling—transistor sizes shrank, but chip speeds no longer got quicker and their power consumption was now an issue. To keep improving performance, designers started arranging logic gates and other elements of their chips in multiple, connected processing units, or “cores”. With multiple cores, a processor can run many applications simultaneously or run a single application faster by splitting it into parallel streams.
This allowed performance to keep climbing even though the speed at which the switches worked was no longer increasing. But it did not solve the problem that the power used by each transistor was no longer falling. As the transistor count continued to rise, chip designers shut down parts of the chip, known as dark silicon, to prevent waste heat from melting it.
Getting around the problem of leakage current meant abandoning the old structure for transistors, in which the conducting channel sat flush to the surface of the chip and the controlling gate sat on top of it. In 2011 Intel introduced a design in which the channel stood proud, like a fin above water, and passed through the gate, not below it (see diagram). This allowed the gate to exert greater control over the channel, even when off. These “finFETs” allowed chipmakers to continue shrinking their transistors. The new transistors leaked less current and consumed about half as much power as the previous generation. Most leading-edge processes now have two or three fins per transistor to boost speed. FinFETs allowed the gate length to shrink further, to around 16nm. But only so many fins can be placed side by side.
To shrink the gate length further, the next step is to lift the channel off the surface of the chip altogether, so that the gate surrounds it on all sides. Samsung, a South Korean giant, was the first to build such transistors, called “gate all around” (GAA), in its latest chips. Intel and TSMC are expected to follow soon. IMEC, a chip-research organisation in Belgium, expects GAA to take the industry to the end of this decade, at which point gate lengths will approach the smallest feature size that can be etched with existing techniques.
One contender to replace silicon is the carbon nanotube
Beyond this point the only way to increase transistor density is to redesign chips so that some of the transistors which used to sit side by side are instead stack one atop the other. Going three-dimensional allows chipmakers to pack in more gates than the horizontal approach. Intel, for example, says that by stacking transistors it can build the simplest kind of logic gate, an inverter, in half the space usually needed.
Even with stacked transistors, the need to squeeze persists. Once a transistor’s gate length approaches 10nm, the thickness of the silicon channel along which the current passes through the gate needs to be less than 4nm, making leakage issues even more pronounced. The industry’s answer to this is to replace silicon with materials available in sheets of almost no thickness at all. Circuits made of materials just a few nanometres thick—the width of a few atoms—could allow chipmakers to shrink transistors without concern about current leaking through when they are off.
Thinning out
Among the two-dimensional (2D) contenders to replace silicon are materials called transition metal dichalcogenides (TMDs) which can be prepared in layers just three atoms thick. Of the hundreds of TMD semiconductors that could replace silicon, three look most promising—molybdenum disulfide, tungsten disulphide and tungsten diselenide.
But such 2D materials have difficulties to overcome before they can challenge silicon. The first is that the thinness of the materials makes them hard to connect with metal wiring. Another is reliably fabricating chips using these materials across a 300mm wafer, the standard size for chip fabrication. Also, chip design relies on two different types of transistor. Making either type is easy in silicon, whereas the new materials tend to be better suited to just one type.
Another contender to replace silicon is the carbon nanotube (CNT), a rolled-up sheet of carbon atoms that forms a cylinder with a diameter of 1.5nm (six times the diameter of a water molecule). A CNT transistor is built like an ordinary transistor with source, drain and gate terminals made of regular semiconductor. But the channel is made up of tiny, parallel nanotubes instead of the silicon channel in an ordinary transistor. The smooth structure of the nanotube allows electric charge to be switched on and off three times faster than through a silicon channel. The thinness of the channel also allows the gate more control over the channel, reducing leakage current and making it more energy efficient.
Eric Pop of Stanford University believes that foundries are leaning towards 2D semiconductors over CNTs, because they are easier to manufacture and integrate with silicon. Though CNTs could offer superior performance and are ideal for GAA transistors, they are harder to control due to manufacturing challenges.
Nanotubes are not easy to build. CNTs are prone to imperfections in the fabrication process which change their electrical properties. Most turn out as semiconductors that turn on and off depending on the gate voltage. About a third are metallic structures that are on all the time and cannot be controlled by the gate. And growing a group of parallel nanotubes as clear parallel lines between the source and drain is hard.
In 2013 Max Shulaker, now at MIT, with Subhasish Mitra and Philip Wong, both of Stanford University, built the first microprocessor using CNT transistors. The researchers designed an “imperfection-immune” processor that functions even if a certain number of CNTs misbehave. By 2019 Mr Shulaker had devised a microprocessor built with 14,000 CNT transistors (half the number found in the 8086, a chip released by Intel in 1978). In 2023 researchers at Peking University built a transistor using CNTs on manufacturing technology that can be scaled down to the size of a 10nm silicon node. The results may seem basic, but they underscore the potential of CNTs as an alternative to silicon.
In 1959 Richard Feynman, a physicist, gave a lecture that presaged the nanotechnology era. He wondered, “What would happen if we could arrange the atoms one by one the way we want them?” With semiconductor device features now atomic lengths, the world has its answer: build smaller transistors. ■
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